Design and Simulation of Radix-8 Booth Encoder Multiplier for Signed and Unsigned Numbers

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Abstract–This paper presents the design and simulation of signed-unsigned Radix-8 Booth Encoding multiplier. The Radix-8 Booth Encoder circuit generates n/3 the partial products in parallel. By extending sign bit of the operands and generating an additional partial product the signed of unsigned Radix-8 BE multiplier is obtained. The Carry Save Adder (CSA) tree and the final Carry Look ahead (CLA) adder used to speed up the multiplier operation. Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. The simulation is done through Verilog on xiling13.3 platform which provide diversity in calculating the various parameters.

Keywords: Array multiplier, Baugh-Woolley multiplier, Braun array multiplier, CLA, CSA, Radix-8 Booth Encoding multiplier, Signed-unsigned


BOOTH ENCODER

Booth’s algorithm involves repeatedly adding one of two predetermined values to a product P, and then performing a rightward arithmetic shift on P.Radix-8 Booth encoding is most often used to avoid variable size partial product arrays. Before designing Radix-8 BE, the multiplier has to be converted into a Radix-8 number by dividing them into four digits respectively according to Booth Encoder Table given afterwards. Prior to convert the multiplier, a zero is appended into the Least Significant Bit (LSB) of the multiplier

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PROPOSED SIGNED UNSIGNED RADIX-8 BOOTH ENCODER MULTIPLIER


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